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We provide professional design support services to our customers, which include:
| Technical Info |
 Libraries |
| Design kits (PDK, DRC,LVS/ERC,LPE,PRE) |
| Design rules (TDR,EDR) |
| Process specifications |
| ESD data |
| SPICE models | |
| Technical consultation and service |
provides consultation to any customer's technical enquiry including design kits, libraries, IP design for
Power IC and so on. | |
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The libraries include:
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A. 0.35um Libraries |
| CSMC 0.35um Polycide logic SPQM CMOS Process. |
354 standard core cells and 98 inline I/O pads, 98 stagger I/O pads, 6 PCI I/O pads, 56 5v power inline
I/O pads. |
| Variety of I/O buffers, CMOS, TTL, SCHMITT with 5v tolerance. |
| Accurate timing characterization. |
| Routable for 3 and 4 metal. |
| Drive strength 2, 4, 8, 12, 16mA. |
| Latch-up performance: 400mA. |
| ESD protection:2.0kV HBM. |
B. 0.5 m Libraries |
| CSMC 0.5um Mixed Signal DPTM CMOS Process. |
| 284 standard cells and 71 I/O pads. |
| Mixed 3.3/5v interface. |
| Variety of I/O buffers, CMOS, TTL, SCHMITT with 5v tolerance. |
| Accurate timing characterization with Synopsys tools. |
| Support most of the EDA tools including Synopsys, Cadence, Mentor. |
| Separate digital library for 2 and 3 metal routing. |
| Drive strength 2, 4, 8, 12, 16, and 24mA. |
| Latch-up performance: 500mA. |
| ESD protection:2.5kV HBM. | |
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A PDK (Process Design Kit) contains the process technology and necessary information for device-level design in the Cadence DFII environment. Our PDK includes: |
| A. 0.5um Mixed Signal PDK |
| B. 0.5um HV PDK | |
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