CSMC-SERVICE-Design Support-EDA

HOME SITEMAP CONTACT | 简体繁體

HOME	CONTACT				CLOSE
ABOUT	Overview	Milestones	Vision & Mission	Key Facts	Social Responsibility
TECHNOLOGIES	Standard Analog	Power IC	Mixed-Signal/RF	Power Discrete
	0.35um 0.5um 0.6um 0.8um	0.18um 0.25um 0.5um 1.0um	0.13um 0.15um 0.18um	Trench Planar
SERVICE	E-service	Design Support	Prototyping Support	Third Party Service	PO Retrieval System
		Libraries/PDKs IP Alliance Design Handbook EDA	MPW Service	MASK service Testing service Assembly service
MANAGEMENT	Manufacturing	Quality	ESH System
		Quality Policy Quality System Reliability & Failure Analysis IP Protection
NEWS	Press Release	In The News
CAREER	Human Resource	CSMC Map

ABOUT

Overview

Milestones

Vision & Mission

Key Facts

Social Responsibility

TECHNOLOGIES

Standard Analog

0.35um

0.5um

0.6um

0.8um

Power IC

0.18um

0.25um

0.5um

1.0um

Mixed-Signal/RF

0.13um

0.15um

0.18um

Power Discrete

Trench

Planar

SERVICES

E-service

Design Support

Libraries/PDKs

IP Alliance

Design Handbook

EDA

Prototyping Support

MPW Service

Third Party Service

MASK Service

Testing Service

Assembly Service

PO Retrieval System

MANAGEMENT

Manufacturing

Quality

Quality Policy

Quality System

RA/FA

IP Protection

ESH System

NEWS

Press Release

In The News

CAREER

Human Resource

CSMC Map

SERVICES

EDA

CSMC keeps an intense and close collaboration with major electronic design automation (EDA) vendors to jointly develop design kits with them. So we can meet our customer‘s various design needs perfectly.

Reference Flow

Synopsys

CSMC-SNPS 180/130nm Reference Flow

Empyrean

CSMC-Empyrean reference IC design flow

DownLoad：

CSMC-SNPS 180/130nm Reference Flow

CSMC-Empyrean reference IC design flow

Physical Verification Tools

Tech. Node	Process	Process Description	CALIBRE	ASSURA	DIVA	DRACULA	HERCULES	Argus
0.13µm	Mixed-signal/RF	P-sub,1.2V/3.3V Including RF	√
0.16µm	Logic	P-sub,1.8v/3.3V	√
0.16µm	Mixed-signal/RF	P-sub,1.8v/3.3V, including RF	√				√
0.18µm	Logic	0.18, p-sub, 1.8v/3.3V	√
0.18µm	Mixed-signal/RF	0.18, p-sub,1.8v/3.3V, including RF	√	√			√
0.35µm	Flatcell	0.35um 5V SPQM flatcell,0.7*0.7 cell,single metal,4 metal,p-sub,polyside,for 5V	√	√		√
		0.7*0.7Flat cell Single metal, P-sub, 3.3V/5V Polycide	√	√		√
		0.63*0.63 Flat cell dual gate oxide, P-sub, 3.5V/5V.	√
	Mixed-Signal	P-sub, 3.3V/5V	√			√		√
0.5FEOL /0.35BEOL	Mixed-Signal	0.5FEOL/0.35BEOL	√			√
		0.5FEOL/0.35BEOL 1.8fF/um^2	√			√
		Plain-poly, 3~5V	√
0.5µm	Mixed-Signal	Enhance Analog for 5V	√
		P-Sub,5V, with PIP/High P2/LVt/Depletion	√	√	√	√		√
		P-Sub,5V, with PIP/High P2/LVt/Depletion 1.8FF Cpip	√			√
	HV	P-sub,40V/25V process	√	√	√	√
		P-sub,Deep Nwell 5V process	√	√	√	√
		P-sub,5V/18V process				*
	BCD	0.5µm 15V(VGS)/15V(VDS) DPTM BCDMOS Process	√	√	√	√
		0.5µm 5V(VGS)/15V(VDS) DPTM BCDMOS Process	√	√	√	√
		0.5µm 5V(VGS)/25V(VDS) DPTM BCDMOS Process	√	√	√	√
		0.5µm 25V(VGS)/25V(VDS) DPTM BCDMOS Process	√	√	√	√
		0.5µm 5V(VGS)/40V(VDS) DPTM BCDMOS Process	√			√
		0.5µm FEOL 0.6µm BEOL				√
		P-sub,18V/20V thick_ox BCDMOS process	√	√	√	√
		P-sub,5V/20V thin_Gox BCDMOS process	√	√	√	√
		P-sub,5V/40V thin_Gox BCDMOS process	√	√	√	√
		P-sub,25V/40V thick_Gox BCDMOS process	√	√	√	√
0.6µm	Logic	P-sub,5V,plain poly, before N-ROM				#
		P-sub,LV,plain poly, before N-ROM				#
		N-sub,5V,N-ROM before plain poly				#
	Mixed Signal	P-sub, 5V, PIP/High P2				*
	Mixed Signal	P-sub, 5V, PIP/High P2,LVt, Depletion				*
	HV	N-sub, 5V-18V				*
1.0µm	MGLV	N-Sub,1.5-5V	√			√
	MGLV	N-Sub,3.0-5V	√			√
	HV	P-sub,5V/40V	√			√
		P-sub,5V/40V, 0.5µm backend, and thick Al2 is option	√			√
		P-sub,5V/25V, 0.5µm backend, and thick Al2 is option(HV GOX 600A)	√			√
2.0µm	36V	DN, Nitride Cap, 1M	√
	36V	DN, Nitride Cap, P-, P+, 1M	√
	18V (5µm Tepi)	DN,SiN Cap, 1M(5µm EPI)	√

√ Provide DRC, LVS, RC xtraction.
* Provide DRC, LVS only.
#Provide DRC only.