CSMC provides ARM 7-track Library and Verisilicon 9-track Library on both 0.13µm and 0.18µm process, which include standard cell, I/O and memory compilers.

In addition, CSMC also provides 0.5µm/0.35µm Mixed-signal, 0.5µm Bipolar-CMOS-DMOS and 0.5µm High voltage process standard cell and I/O cell Library, 0.18µm Mixed-Signal 7-track&9-track standard cell Library with different routing pitches to help customers to achieve optimal die sizes and effective cost. These Libraries offer robust ESD protection. All of them support Cadence and Synopsys ASIC SOC design flow.

All these Libraries offer customers a choice of Library implementation options. CSMC facilitates the relationship between customers and Library vendors to ensure successful tape-out, and faster time-to-market.

 

 Libraries at CSMC

Tech.Node	Process	Available Libraries
0.13µm G	7 Track Metro Library	7 Track Standard Cell Library, PMK, Inline I/O, Stagger I/O, Memory Compiler
	9 Track Library	9 Track Standard Cell Library, Inline I/O, Stagger I/O, Memory Compiler
0.13µm LP	9 Track Library	9 Track Standard Cell Library, Inline I/O, Stagger I/O, Memory Compiler
0.18µm G	7 Track & 9 Track Library	7 Track & 9 Track Standard Cell Library, Inline I/O, Stagger I/O, DUP I/O,RF I/O Memory Compiler
0.35µm	9 Track Library	9 Track Standard Cell Library, Inline I/O, Stagger I/O
0.5µm MS	9 Track Library	9 Track Standard Cell Library, Inline I/O
0.5µm BCD	9 Track Library	9 Track Standard Cell Library, Inline I/O

Tech.Node	Available PDKs based on Cadence Design Tools
0.5µm	Mixed-Signal,Mixed-Signal High Cap.;BCD;High Voltage;0.5µm FE 0.35µm BE;0.5µm FE 0.35µm BE High Cap.
0.35µm	Mixed-Signal
0.18µm	Mix-Signal/RF

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Tech.Node	Available PDKs based on Empyrean‘s Design Tools-Aether
0.5µm	Mixed-Signal
0.35µm	Mixed-Signal