Power IC-1.0um
 1.0µm 25/40V HV
1.0 Micron 25V or 40V High Voltage CMOS Technology for high voltage Product Applications
 
 Overview
      10HV是华润上华的标准高压工艺平台之一。是以较少光刻层数实现的经济高压工艺,工艺特征为1.0µm 线宽,单层多晶,双层金属,应用于数模混合的高压产品,工艺平台提供常规及隔离的5V低压CMOS,25V或40V高压CMOS器件,以及多晶高阻和齐纳二极管等器件。为了节省芯片面积,工艺提供1.0µm 前端0.5µm后端设计规则。工艺平台详尽的设计规则,精确的SPICE模型,DRC和LVS工具包可以支持主要的EDA软件工具。
 
 Key Features
- 5V logic layout & performance compatible with the industry standard
- 1.0 micron front-end, 1.0 micron or 0.5 micron back-end design rule
- Epi process for isolated devices
- Modular concept (HR/ Zener / BJT / Special require)
- Vgs/Vds=5V/25 or Vgs/Vds=5V/40V,Vgs/Vds=25V/25 or Vgs/Vds=40V/40V HVCMOS
- High value poly resistor
- I/O cell library with 2KV HBM ESD protection levels
- Typical and worst-case models: BSIM3v3.2 ---MOS; Sub-circuit model---RES&CAP
 
 Applications
- LCD driver
- LED driver
- Power management product
- Battery protection IC
- CCFL inverter
 
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 1.0µm 700V BCD
1.0 Micron 700V High Voltage CMOS Technology for high voltage Product Applications
 
 Overview
      10HV700是华润上华的标准高压工艺平台之一,是以较经济的光刻层数实现700V高压工艺,特别合适离线式电源(AC/DC)和LED 驱动产品设计,特征为1.0µm 线宽,单层多晶,双层金属,工艺平台提供常规及隔离的5V低压CMOS,40V中压CMOS器件,700V LDMOS,700V HV 耗尽管,700V JFET器件,以及多晶高阻和齐纳二极管等器件。为了节省芯片面积,工艺提供0.5µm后端设计规则。工艺平台详尽的设计规则,精确的SPICE模型,DRC和LVS工具包可以支持主要的EDA软件工具。
 
 Key Features
- 5V logic layout & performance compatible with the industry standard
- 1.0 micron front-end, 0.5 micron back-end design rule
- Epi process for isolated devices
- Modular concept (HR/ Zener / BJT /700V Dep. NMOS/ 700V JFET/ Special require)
- 700V LDMOS. BVds>750V
- 700V Dep. NMOS, Voff: -5.0V/-5.8V, BV>750V
- JFET Voff: -9V/-25V
- High value poly resistor; 1K or 3K  
 
 Applications
- Off-line power (AC/DC)
- LED driver
 
 
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 1.2µm 5V SOI
1.2 Micron Modular 5V SOI Technology for Analog Product Applications
 
 Overview
      1.2um 5V SOI 是华润上华的SOI工艺之一。采用顶层硅厚度为2900A,埋氧厚度为4000A的SOI 圆片。工艺特征为1.2µm 线宽,单层多晶,双层金属,应用于逻辑电路产品,工艺平台提供常规5V NMOS, PMOS 器件。
 
 Key Features
- 5V logic layout & performance compatible with the industry standard
- 1.2um single poly, double metal CMOS basic process.
- SOI wafer for all devices
- salicide backend process
 
 Applications
- SRAM
 
 
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 1.5µm 200V SOI
1.5 Micron Modular 200V SOI Technology for Analog Product Applications
 
 Overview
      1.5um 200V SOI 是华润上华的标准高压工艺之一。采用7um厚的BESOI 圆片,工艺特征为1.5µm 线宽,单层多晶,双层金属,应用于大电流驱动的高压产品,工艺平台提供常规5V低压CMOS, 200V IGBT/NLDMOS/PLDMOS/HV diode,以及齐纳二极管等器件。为了节省芯片面积,工艺提供1.5µm 前端0.5µm后端设计规则。
 
 Key Features
- 5V logic layout & performance compatible with the industry standard
- 1.5 micron front-end, 1.5 micron or 0.5 micron back-end design rule
- SOI wafer for all devices
- Vgs/Vds=5V/170V IGBT;Vgs/Vds=5V/170V NLDMOS; Vgs/Vds=170V/170V PLDMOS
- Provide high temperature models - (5VCMOS,NLDMOS,PLDMOS,IGBT,RES) 
 
 Applications
- PDP driver
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